diff options
| author | Jakob L. Kreuze <zerodaysfordays@sdf.org> | 2022-04-15 18:20:34 -0400 |
|---|---|---|
| committer | Jakob L. Kreuze <zerodaysfordays@sdf.org> | 2022-04-15 18:20:34 -0400 |
| commit | 119d15709be940524fff65f8d5e728d00454526c (patch) | |
| tree | 3f2f33a57dcff88acd68985f8d1928c4ccac8ec7 /sys-boot/u-boot/files/0003-Enable-the-power-LED-during-early-startup.patch | |
| parent | f9f0f9deac28886cd5661a72a671a6bfdcbcbcb8 (diff) | |
Add sys-boot/u-boot
Diffstat (limited to 'sys-boot/u-boot/files/0003-Enable-the-power-LED-during-early-startup.patch')
| -rw-r--r-- | sys-boot/u-boot/files/0003-Enable-the-power-LED-during-early-startup.patch | 50 |
1 files changed, 50 insertions, 0 deletions
diff --git a/sys-boot/u-boot/files/0003-Enable-the-power-LED-during-early-startup.patch b/sys-boot/u-boot/files/0003-Enable-the-power-LED-during-early-startup.patch new file mode 100644 index 0000000..a2e811c --- /dev/null +++ b/sys-boot/u-boot/files/0003-Enable-the-power-LED-during-early-startup.patch @@ -0,0 +1,50 @@ +From 08e8ace48b5c3a31b44661ef22a8b8a459906d7e Mon Sep 17 00:00:00 2001 +From: Nadia Holmquist Pedersen <nadia@nhp.sh> +Date: Sat, 20 Jun 2020 01:49:49 +0200 +Subject: [PATCH 3/3] Enable the power LED during early startup + +--- + arch/arm/mach-rockchip/rk3399/rk3399.c | 12 +++++++++++- + 1 file changed, 11 insertions(+), 1 deletion(-) + +diff --git a/arch/arm/mach-rockchip/rk3399/rk3399.c b/arch/arm/mach-rockchip/rk3399/rk3399.c +index 4fda93b152..e24b39486d 100644 +--- a/arch/arm/mach-rockchip/rk3399/rk3399.c ++++ b/arch/arm/mach-rockchip/rk3399/rk3399.c +@@ -19,6 +19,8 @@ + #include <asm/arch-rockchip/hardware.h> + #include <linux/bitops.h> + #include <power/regulator.h> ++#include <dt-bindings/gpio/gpio.h> ++#include <dt-bindings/pinctrl/rockchip.h> + + DECLARE_GLOBAL_DATA_PTR; + +@@ -119,8 +121,8 @@ void board_debug_uart_init(void) + struct rk3399_grf_regs * const grf = (void *)GRF_BASE; + #ifdef CONFIG_TARGET_CHROMEBOOK_BOB + struct rk3399_pmugrf_regs * const pmugrf = (void *)PMUGRF_BASE; +- struct rockchip_gpio_regs * const gpio = (void *)GPIO0_BASE; + #endif ++ struct rockchip_gpio_regs * const gpio = (void *)GPIO0_BASE; + + #if defined(CONFIG_DEBUG_UART_BASE) && (CONFIG_DEBUG_UART_BASE == 0xff180000) + /* Enable early UART0 on the RK3399 */ +@@ -153,6 +155,14 @@ void board_debug_uart_init(void) + spl_gpio_set_pull(&pmugrf->gpio0_p, GPIO(BANK_B, 4), GPIO_PULL_NORMAL); + #endif /* CONFIG_TARGET_CHROMEBOOK_BOB */ + ++ { ++ // set GPIO0_A2/B3 to GPIO_ACTIVE_HIGH ++ // set GPIO0_A2/B3 to OUTPUT ++ int mask = (1UL << RK_PA2) | (1UL << RK_PB3); ++ setbits_le32(&gpio->swport_dr, mask); ++ setbits_le32(&gpio->swport_ddr, mask); ++ } ++ + /* Enable early UART2 channel C on the RK3399 */ + rk_clrsetreg(&grf->gpio4c_iomux, + GRF_GPIO4C3_SEL_MASK, +-- +2.27.0 + |