From 2346e752d01524c40cc1c4671247798c89802de9 Mon Sep 17 00:00:00 2001
From: "Jakob L. Kreuze" <zerodaysfordays@sdf.lonestar.org>
Date: Wed, 1 Jan 2020 14:00:18 -0500
Subject: Implement register arithmetic instructions.

---
 main.myr | 52 ++++++++++++++++++++++++++++++++++++++++++++++++++++
 1 file changed, 52 insertions(+)

diff --git a/main.myr b/main.myr
index cf6897b..d7fc392 100644
--- a/main.myr
+++ b/main.myr
@@ -117,8 +117,60 @@ const main = {
         // LD
         | 0x6:
             reg[opcode & 0x0f] = arg
+        // ADD (without overflow)
+        | 0x7:
+            reg[opcode & 0x0f] += arg
+        | 0x8:
+            match arg & 0x0f
+            // LD
+            | 0x0:
+                reg[opcode & 0x0f] = reg[(arg & 0xf0) >> 8]
+            // OR
+            | 0x1:
+                reg[opcode & 0x0f] |= reg[(arg & 0xf0) >> 8]
+            // AND
+            | 0x2:
+                reg[opcode & 0x0f] &= reg[(arg & 0xf0) >> 8]
+            // XOR
+            | 0x3:
+                reg[opcode & 0x0f] ^= reg[(arg & 0xf0) >> 8]
+            // ADD
+            | 0x4:
+                if (0xff - reg[opcode & 0x0f]) < reg[(arg & 0xf0) >> 8]
+                    reg[0xf] = 1
+                else
+                    reg[0xf] = 0
+                ;;
+                reg[opcode & 0x0f] += reg[(arg & 0xf0) >> 8]
+            // SUB
+            | 0x5:
+                if (0xff - reg[opcode & 0x0f]) < reg[(arg & 0xf0) >> 8]
+                    reg[0xf] = 1
+                else
+                    reg[0xf] = 0
+                ;;
+                reg[opcode & 0x0f] -= reg[(arg & 0xf0) >> 8]
+            // SHR
+            | 0x6:
+                reg[0xf] = reg[opcode & 0x0f] & 1
+                reg[opcode & 0x0f] >>= 1
+            // SUBN
+            | 0x7:
+                if (0xff - reg[(arg & 0xf0) >> 8]) < reg[opcode & 0x0f]
+                    reg[0xf] = 1
+                else
+                    reg[0xf] = 0
+                ;;
+                reg[opcode & 0x0f] = reg[(arg & 0xf0) >> 8] - reg[opcode & 0x0f]
+            // SHL
+            | 0xe:
+                reg[0xf] = reg[opcode & 0x0f] & (1 << 7)
+                reg[opcode & 0x0f] <<= 1
+            | _: std.die("unimplemented opcode\n")
+            ;;
         | _ : std.die("unimplemented opcode\n")
         ;;
+        pc += 2
     ;;
 
     sdl.update(tex, (gfx[:] : void#), 64)
-- 
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